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Abstract:
This project concerns the design and implementation of a control and measurement system for an elevation over azimuth antenna on a Navy Jammer pedestal. The control system is run using LabVIEW from the parallel port of a PC, through the interfaced drive electronics. The measurement system involves acquiring data signals from the synchros on the pedestal and capturing the resulting data in a GUI based interface with a North Atlantic Industries, 76CS1 PCI S/D data acquisition card.
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Abstract:
This thesis describes the design, implementation, production and testing of a 3 GSPS ADC board for the iBOB reconfigurable hardware platform. The ADC board was developed for use in the KAT project.
The design phase consisted of generating a high level, block diagram of the system and then creating the detailed circuit diagram, which was implemented in the PCB layout. Firmware for the iBOB was also developed to support the ADC board.
Following the successful completion of the design phase the board was sent to be manufactured. This took longer than expected, which delayed the remainder of the project. The board was populated and some basic tests were conducted.
Due to problems with the manufacture of the board and the time con- straints, thorough testing of the board did not take place. However, a testing plan for the system was developed and a list of possible improvements has been included.
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Abstract:
This thesis investigates the performance of the Cell Broadband Engine (Cell BE) Architecture for executing a Polyphase Filter Bank algorithm, used for efficient signal channelisation.
The heterogeneous multi-core architecture of the Cell BE is introduced and important considerations for developing programs for the Cell BE are discussed. The Polyphase Filter Bank DFT channeliser is discussed in depth, and the process of mapping this algorithm onto the Cell BE processor architecture is shown.
An evaluation of the performance of the Polyphase Filter Bank algorithm on the Cell BE processor is presented with results obtained from the Sony Playstation 3 and the IBM Full System Simulator. The effect of the parameters of the algorithm on the performance is investigated. The Cell BE processor is shown to be efficient for some algorithms, and the factors that have both positive and negative impact on its performance are presented.
The current implementation of the Cell BE processor has some important limitations for use in scientific computation.
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Abstract:
This report details the results of a design process followed in designing an automated Sun photometer system. This refers specifically to an integration of an electronic Sun photometer within a system capable of continuously positioning this photometer such that it is aimed directly at the Sun without user intervention.
The manner in which this is done, its defects and possible solutions to such are outlined here along with the theory behind and for this instrument. A MC9S12NE64 microcontroller is used as the basis for system control and is therefore described in basic detail also.
The final design arrived at for this system; its implementation and intended implementation are described. For the most part this serves as a design document from which a complete system could be developed.
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Abstract:
This report aims to investigate and test the application of graphics cards to common signal processing tasks. Recent developments in graphics processor technology have made it possible to use these processors for more general computing tasks than simply rendering graphics.
The report begins by introducing the graphics card and pipeline. It then moves on to an investigation of the tools that are available to facilitate general purpose computation from low level shader languages to high level software development kits. This is followed by an investigation of available libraries that perform the fast Fourier transform on the GPU.
Next, the CUDA Toolkit is used to test the fast Fourier transform on the GPU. The associated CUFFT library is used for the task and the CPU benchmark is run using the FFTW library’s BenchFFT program. The GPU implementation was found to be significantly faster in execution speed than the CPU implementation for large transform sizes. The accuracy on the GPU was found to be good as well.
This is followed by the implementation of simple filters on the graphics card. The results obtained are compared with similar implementations on the CPU based on their performance and the accuracy. Here it was found that the CPU implementation performed far better than the GPU due to the slow memory accesses. Accuracy was good for finite impulse response filters but bad for infinite impulse response filters.
To conclude, graphics processors were found to be extremely fast when calculating FFTs and extremely inefficient for the filters. This dichotomy is caused due to the nature of programming for a GPU where memory accesses to device memory take significantly more clock cycles than to local registers. It is conceivable that an optimised GPU filter algorithm would surpass the CPU implementation for filters with a large number of taps. This brings into focus the importance of designing algorithms from the ground up to take full advantage of the power of the graphics card.
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Abstract:
Passive Coherent Location is a method of radar which exploits so-called ’illuminators of opportunity’ in order to detect targets.
The implementation of the signal processing aspects on a PC of a PCL system is explored, as well as the possible performance enhancements from using a consumer-grade graphics card’s GPU as a co-processor for the processing tasks.
A number of aspects of the GPU’s performance are explored, specifically regarding memory transfer capabilities.
While the GPU was found to provide a significant speed advantage in terms of processing time, its performance is still limited by current memory technology.
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Abstract:
Embedded systems are taking on more complicated tasks as the processors involved become more powerful. As the number of transistors per area of silicon increases in a fairly predictable fashion as forecast by Gordon E Moore in 1965 we have more resources available for features that speed up development and time to market.
The extra computer resources being fitted into the same space allows some embedded projects to consider an operating system while still maintaining the required speed of response. Operating systems can greatly reduce the time to market of an embedded project and save the developers handling chores like race conditions, multitasking and hardware access.
The partitioning decision in any project as to which portion of the project to implement in hardware and which portion to implement in software has always been fundamental to embedded projects. The decision is usually based on the project's performance requirements and hardware used when software solutions are not fast enough. Software provides better versatility and flexibility and with the increase in performance in the computing field software can take on more and still have resources left over for improving code structure and development features.
Altera provide soft-core processors implemented on a Field Programmable Gate Array and the performance of these processors have become competitive with conventional processors.
Using the Altera Cyclone 1 evaluation board and Cyclone 2 development board both running the NIOS2 soft-core processor, this thesis investigates the versatility and performance as well as the time-to-market which this soft-core processor technology brings to the embedded systems field.
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This page was last updated in September 2008 (RL)